1. Field of the Invention
The present invention relates to CMOS output buffers, and more particularly to output buffers with controlled slow slew rates that are relatively independent of capacitive loads and draw no DC power.
2. Background Information
Output buffers must be fast enough to match the high data rates of the signals the buffer is sending, but they must be slow enough to not cause EMI (ElectroMagnetic Interference) with nearby electronics. “Fast enough” and “slow enough” refers to the speed of rising and falling edges. Slew rates,” edge “rise and fall times,” and other such terms as may be used in the art may have different definitions, but they are used interchangeably herein.
Output load capacitance has a substantial effect of slew rates. With a 20/1 capacitive load variation, prior art slew rates may vary proportionally or even more depending on the equivalent resistance operating with the load capacitance.
FIG. 1 illustrates a prior art output buffer's voltage profiles with 10 pF, 75 pF and 150 pF capacitive loads. So, for example, if a square wave is input, the output edge rise and fall times 10 are about one nanosecond with a 10 pF load capacitor, and those times increase to twenty-four nanoseconds with a 150 pF load capacitor. In this example a 15 to 1 increase in output capacitance results in a 24 to 1 edge slow down.
Limitations of the prior art include one nano-second edge times that may generate EMI noise adversely affecting other electronics, and, with large load capacitors, slow edge rise and fall times may not meet the data rates of the signals involved.
U.S. Pat. No. 5,748,019 ('019) owned by VLSI Technologies, Inc. of San Jose, Calif. compensates for load capacitance. The '019 reference, however, uses reference voltage supplies, current sources and capacitive feedback. But the '019 use voltage references, that constantly drain DC current, and capacitors and current sources that distinguish this reference from the present invention.
It would be advantageous to have an output buffer with an output edge time that remained about constant with capacitive load variations; that was slow enough to not cause EMI disturbances, but was fast enough to meet the data rates of the circuitry involved. For example, an output buffer with an edge rising and falling time of about 20 to 40 nanoseconds when loaded with 10 to 200 pF capacitors, respectively.